1. Technical Field
The present disclosure relates to analog to digital converting technology and, more particularly, to a single slope analog to digital converter using a hysteresis property and an analog to digital converting method.
2. Discussion of Related Art
A single slope analog to digital converter, that is, single slope ADC, receives and compares an input signal having a constant voltage level to a ramp signal, and converts a time or a time-point, when a voltage level of the input signal and a voltage level of the ramp signal become the same, into a digital signal or a digital code.
FIG. 1 is a block diagram of a conventional single slope ADC. The single slope ADC 10 includes a comparator 12, an inverter 14, and a code generator 16.
The code generator 16 can include a counter (not shown). The counter starts counting in response to a clock signal CLK from a time when a ramp signal RAMP starts ramping and outputs an n-bit (n is a natural number) digital value as a result of the counting. Therefore, the code generator 16 outputs the n-bit digital value at a time or time-point, when a voltage level of the input signal INPUT and a voltage level of the ramp signal RAMP become the same, as a digital signal (or a digital code).
FIGS. 2A and 2B illustrate waveforms of an output signal of the comparator 12 of the single slope ADC 10 and an input signal of the code generator 16 illustrated in FIG. 1.
Referring to FIGS. 1, 2A, and 2B, when the comparator 12 compares a voltage level of the input signal INPUT with a voltage level of the ramp signal RAMP, the comparator 12 outputs an output signal that includes noise of the ramp signal RAMP, as well as noise introduced by the comparator 12.
Even if not considering noise generated from the inverter 14, noise of the ramp signal RAMP and noise from the comparator 12 are inputted to the code generator 16 as they are through the inverter 14 and, thus, noise of the ramp signal RAMP and noise from the comparator 12 directly affect a digital code OC outputted from the code generator 16. The digital code OC can be an n bit digital value outputted from a counter.
FIG. 2A illustrates waveforms of an ideal output signal of a comparator 12 or an output signal of a comparator 12, which does not introduce any noise at all, and an input signal of a code generator 16. In this case, the code generator 16 outputs a digital code CODE1 indicating a time or time-point when a voltage level of an input signal INPUT and a voltage level of a ramp signal RAMP become the same.
FIG. 2B illustrates waveforms, however, of an output signal of a comparator 12 including noise and an input signal of a code generator 16 reflecting that noise. In this case, the code generator 16 outputs a digital code CODE2, not digital code CODE1, due to the effect of the noise included in the output signal of the comparator 12. The output code noise is represented by the difference between digital code CODE2 and digital code CODE1.
In other words, the code generator 16 does not exactly convert the time or time-point, when the voltage level of the input signal INPUT and the voltage level of the ramp signal RAMP become the same, as a digital code due to the effect of digital code noise generated on the ground of basis of noise included in an output signal.
In addition, in case that a feature of the comparator 12 cannot be optimized, for example, is not able to eliminate noise, due to a limitation of layout areas in a CMOS image sensor, which includes the single slope ADC 10 illustrated in FIG. 1, has a column parallel structure arranged in several columns, the code generator 16 is affected with the noise introduced by the comparator 12.
Accordingly, since the code generator 16 embodied in the CMOS image sensor cannot exactly convert a time or time-point, when a voltage level of the input signal INPUT and a voltage level of the ramp signal RAMP become the same, as a digital code, a performance of the CMOS image sensor is considerably degraded.
Therefore, for improving the performance of the single slope ADC 10 or CMOS image sensor including such a single slope ADC 10, a single slope ADC that can reduce noise generated by a comparator 12 and inputted to a code generator 16 is strongly required